We will identify and observe the defective areas of power devices such as diodes, MOS-FETs, and IGBTs.
We perform optimal preprocessing for power devices such as diodes, MOS FETs, and IGBTs of all sizes and shapes, and identify and observe defective areas through backside IR-OBIRCH analysis and backside emission analysis. ■ Preprocessing for Analysis - Backside Polishing - Supports various sample forms. Si chip size: 200um to 15mm square ■ Defective Area Identification - Backside IR-OBIRCH Analysis / Backside Emission Analysis - IR-OBIRCH Analysis: Supports up to 100mA/10V and 100uA/25V Emission Analysis: Supports up to 2kV * Covers a wide range of defect characteristics such as low-resistance shorts, micro-leaks, and high-voltage breakdown failures. ■ Pinpoint Cross-Section Observation of Leak Areas - SEM/TEM - Select SEM or TEM observation based on the predicted defects, allowing for pinpoint physical observation and elemental analysis of leak defect areas.
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basic information
- Package condition: Opened chip, single chip, back surface polishing of wafer state Si chip size: 200um to 15mm - IR-OBIRCH analysis: Supports up to 100mA/10V and 100uA/25V Sensitivity: Several tens of pA Low magnification maximum field of view: 6.5mm square - Emission analysis: Supports up to 2kV Sensitivity: Several nA Low magnification maximum field of view: 6.5mm square - Specific position accuracy: ±0.3um, sample thickness 1.5um to 0.1um - Mechanical polishing SEM observation: Observation of large damage areas, foreign objects, and extensive areas - Diffusion layer observation: Can be observed near defective areas before TEM sample preparation Pre-treatment may be required depending on the structure - FIB-SEM observation: Observation of cracks, shape abnormalities, and diffusion layers (up to ×50k) - Cross-sectional TEM observation: Destruction of gate oxide film and dislocations (up to 400k)
Price information
We will provide a quote based on the content.
Delivery Time
※It varies depending on the content (express service available).
Applications/Examples of results
- Defects caused by bonding: Attack by foreign substances, cracks due to stress - Defects caused by the IC process: Layer patterning issues, source Al defects, foreign substance contamination, gate oxide film destruction, dislocations - Observation of diffusion layers using FIB-SEM
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Company information
Aites was established in 1993, originating from the quality assurance department of the IBM Japan Yasu office. Based on the technical expertise cultivated through cutting-edge defect analysis and reliability assurance of electronic components at the IBM Japan Yasu office, we have provided various products and services that support the development and manufacturing of semiconductors, displays, organic EL, solar cells, and electronic components to customers both domestically and internationally.
