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  6. TOE 40G IP core for FPGA

TOE 40G IP core for FPGA

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TOE40G-IP

last updated:Jan 30, 2019

デザイン・ゲートウェイ
デザイン・ゲートウェイ
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Achieved 40 times speed 10GbE TCP/IP communication function with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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TOE40Gx2.jpg

TOE 40G IP core for FPGA

TOE40Gx2.jpg
TOE40Gx2.jpg
  • Related Link - http://www.dgway.com/TOE40G-IP_X.html

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basic information

- Supports simultaneous transmission and reception (Full Duplex) of 40GbE over TCP - Pure hardware-wired TCP/IP protocol stack - Single session connection - Supports both server and client modes (passive/active open/close) - High-speed processing for transmission and reception - Supports jumbo frames (during transmission) - Transmission/reception buffer size can be adjusted to optimal points based on consumed resources and performance - User-friendly interface (data I/F is FIFO type, control I/F is register type) - Supports IPv4 - Core can be evaluated on genuine Xilinx/Intel evaluation boards before purchase - Reference project that operates on actual hardware included with the product, with all source code provided except for the core - PC rental available for actual hardware evaluation - Reliable domestic support

Price range

P6

Delivery Time

P3

※A license agreement is required.

Applications/Examples of results

The TOE40G-IP core is the ideal solution for applications that require high-speed transfer of large amounts of data, such as video and storage. (Application examples) ■ Large-scale blade servers (enterprise cloud) ■ NAS (Network Attached Storage) ■ SDN (Software Defined Network) ■ Video editing systems

Detailed information

  • TOE40G-IPblock.jpg

    TOE40G-IP Block Diagram TCP/IP functionality implemented with complete hard logic

Line up(2)

Model number overview
TOE40G-IP-ZUP TOE40G-IP compatible with Zynq Ultrascale+
TOE40G-IP-A10 TOE40G-IP compatible with Arria 10

catalog(3)

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Design Gateway Comprehensive Catalog (Intel Version)

Design Gateway Comprehensive Catalog (Intel Version)

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Design Gateway Comprehensive Catalog (Xilinx Edition)

Design Gateway Comprehensive Catalog (Xilinx Edition)

CATALOG
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CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

PRODUCT
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Company information

デザイン・ゲートウェイ

デザイン・ゲートウェイ

Information and Communications

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Design Gateway is a pioneer in the development and sales of advanced IP cores, with over 30 years of experience in the FPGA industry.

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