NVMe IP core for FPGA

basic information

- Implementation of an application layer to access NVMe PCI Express SSDs - Simple user control interface and FIFO interface for data ports - Built-in 256K byte data buffer in the core constructed with BRAM - Supports six commands - IDENTIFY, WRITE, READ, Shutdown, SMART, Flush - Preparation of evaluation adapter boards AB18-PCIeX16, AB17-M2FMC, AB16-PCIeXOVR - Provision of NVMeG4-IP (built-in version of PCIe Gen4 Soft IP), compatible with devices without PCIe Hard IP (Gen3 version also available) - raNVMe-IP achieves over 500K IOPS random access without a CPU - Compatible with PCIe switches (customized individual support available; please inquire for details) - Access to exFAT/FAT32 file systems possible without a CPU (optional) - Reference project that operates on actual hardware included with the product, with all source code provided except for the core - Reliable domestic support

Price range

Delivery Time

P3

※It is necessary to conclude a license agreement.

Applications/Examples of results

The NVMe-IP core enables connection with various form factor SSDs. For example, by integrating NVMe-IP and data acquisition user logic into an FPGA, it is possible to create a super compact and ultra-fast data acquisition system by recording data to an M.2 SSD. raNVMe-IP achieves over 500K IOPS of random (write) access to high-performance NVMe SSDs without using a CPU. raNVMe-IP is ideal for applications that require multiple simultaneous accesses to NVMe SSDs at peak performance, such as high-speed SSD database search systems.

Detailed information

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  NVMe-IP Block Diagram No CPU or external memory required, optimized PCIe bridge integrated

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