TCP/IP communication functionality can be implemented with pure hardware logic without a CPU!
The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes with a reference design compatible with Xilinx/Altera FPGAs as a standard attachment to the core product, which can help shorten product development time.
Inquire About This Product
basic information
■Supports simultaneous transmission and reception (Full Duplex) of TCP ■Pure hardware-wired TCP/IP protocol stack ■Enables CPU-less system construction by fully hardware-implementing transmission and reception processing ■Supports both server and client modes (Passive / Active open / close) ■Supports jumbo frames ■Configurable buffer size for transmission and reception ■User-friendly interface (Data I/F is FIFO type, Control I/F is register type) ■Supports IPv4 ■Transmission window size supports 4kbyte to 64kbyte (using FPGA internal BRAM) ■Allows pre-purchase core evaluation on Xilinx/Altera evaluation boards ■Includes a reference project that operates on actual hardware with all source code provided except for the core ■PC rental support for actual hardware evaluation ■Reliable domestic support
Price range
Delivery Time
P3
※It is necessary to conclude a licensing agreement.
Applications/Examples of results
The TOE1G-IP core is an ideal solution for applications that require high-speed transfer of large amounts of data, such as video and storage. (Application examples) ■ NAS (Network Attached Storage) ■ Ethernet cameras
Detailed information
-
TOE1G-IP Performance In half-duplex communication with a single direction only, high throughput is achieved even with non-jumbo frames, and performance hardly decreases even in full-duplex bidirectional communication!
Line up（6）
| Model number | overview |
|---|---|
| TOE1G-IP-KT7 | TOE1G-IP compatible with Kintex-7 |
| TOE1G-IP-VT7 | TOE1G-IP compatible with Virtex-7 |
| TOE1G-IP-ZQ7 | TOE1G-IP compatible with Zynq-7000 |
| TOE1G-IP-AT7 | TOE1G-IP compatible with Artix-7 |
| TOE1G-IP-S4 | TOE1G-IP compatible with Stratix IV |
| TOE1G-IP-A5 | TOE1G-IP compatible with Arria V |
catalog（3）
Download All Catalogs
![CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog](https://image.www.ipros.com/public/catalog/image/01/921/544732/IPROS35007459182912551656.jpeg?w=120&h=170)
Company information
Design Gateway is a pioneer in the development and sales of advanced IP cores, with over 30 years of experience in the FPGA industry.