TOE1G-IP core for FPGA

basic information

■Supports simultaneous transmission and reception (Full Duplex) of TCP ■Pure hardware-wired TCP/IP protocol stack ■Enables CPU-less system construction by fully hardware-implementing transmission and reception processing ■Supports both server and client modes (Passive / Active open / close) ■Supports jumbo frames ■Configurable buffer size for transmission and reception ■User-friendly interface (Data I/F is FIFO type, Control I/F is register type) ■Supports IPv4 ■Transmission window size supports 4kbyte to 64kbyte (using FPGA internal BRAM) ■Allows pre-purchase core evaluation on Xilinx/Altera evaluation boards ■Includes a reference project that operates on actual hardware with all source code provided except for the core ■PC rental support for actual hardware evaluation ■Reliable domestic support

Price range

Delivery Time

P3

※It is necessary to conclude a licensing agreement.

Applications/Examples of results

The TOE1G-IP core is an ideal solution for applications that require high-speed transfer of large amounts of data, such as video and storage. (Application examples) ■ NAS (Network Attached Storage) ■ Ethernet cameras

Detailed information

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  TOE1G-IP Performance In half-duplex communication with a single direction only, high throughput is achieved even with non-jumbo frames, and performance hardly decreases even in full-duplex bidirectional communication!

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