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  6. 25G TOE IP core for FPGA

25G TOE IP core for FPGA

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TOE25G-IP

last updated:Oct 13, 2020

デザイン・ゲートウェイ
デザイン・ゲートウェイ
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Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides a performance and bandwidth of 25G, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

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TOE25G-IPblock.jpg

25G TOE IP core for FPGA

TOE25G-IPblock.jpg
TOE25G-IPblock.jpg
  • Related Link - http://www.dgway.com/TOE25G-IP_X.html

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basic information

■Supports simultaneous transmission and reception (Full Duplex) of 25GbE over TCP ■Pure hardware-wired TCP/IP protocol stack ■Single session connection ■Supports both server and client modes (passive/active open/close) ■High-speed processing for transmission and reception ■Supports jumbo frames (during transmission) ■Transmission/reception buffer size can be adjusted to optimal points based on resource consumption and performance ■User-friendly interface (data I/F is FIFO type, control I/F is register type) ■Supports IPv4 ■Standard support for DG's 10G25G EMAC-IP ■Evaluation of the core on genuine Xilinx/Intel evaluation boards before purchase is possible ■Includes a reference project that operates on actual hardware with all source code provided except for the core ■Loan support for PCs for actual hardware evaluation ■Reliable domestic support

Price range

P6

Delivery Time

P3

※A license agreement is required.

Applications/Examples of results

The TOE25G-IP core is the ideal solution for applications that require high-speed transfer of large amounts of data, such as video and storage. (Application examples) ■ Large-scale blade servers (enterprise cloud) ■ NAS (Network Attached Storage) ■ SDN (Software Defined Network) ■ Video editing systems

Detailed information

  • TOE40G-IPblock.jpg

    TOE40G-IP Block Diagram TCP/IP functionality implemented with complete hard logic

Line up(2)

Model number overview
TOE25G-IP-ZUP TOE25G-IP compatible with Zynq Ultrascale+
TOE25G-IP-S10GX TOE25G-IP compatible with Stratix 10 GX

catalog(3)

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Design Gateway Comprehensive Catalog (Intel Version)

Design Gateway Comprehensive Catalog (Intel Version)

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Design Gateway Comprehensive Catalog (Xilinx Edition)

Design Gateway Comprehensive Catalog (Xilinx Edition)

CATALOG
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CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

CPU Low Latency High-Speed Network IP Core [TOE-IP/UDP-IP] Catalog

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Company information

デザイン・ゲートウェイ

デザイン・ゲートウェイ

Information and Communications

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Design Gateway is a pioneer in the development and sales of advanced IP cores, with over 30 years of experience in the FPGA industry.

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