テクノクリエート List of Products and Services

The "Lead Solomon Express" is an error correction encoding/decoding (Encoder/Decoder) IP core that achieves a throughput of over 1 Gbps by processing error location polynomials and error values in a pipeline manner. It supports variable data block lengths. 【Features】 ■ Achieves a throughput of over 1 Gbps ■ Supports variable data block lengths ■ The number of check bits, primitive polynomials, and generator polynomials can be customized according to your requirements. *For more details, please refer to the PDF document or feel free to contact us.

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The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding based on the Reed-Solomon method, used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, as well as the primitive polynomial and generator polynomial, can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.

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The "Multi-Channel Compatible ADPCM Transcoder" is a 64-channel version of the ADPCM transcoder IP for FPGA that complies with ITU-T Recommendation G.726. By combining it with a PCM codec, it can replace the ADPCM codec LSI. 【Features】 ■ ITU-T Recommendation G.726 compliant 32kbps ADPCM transcoder ■ Compatible with both μ-law and A-law ■ Supports 64 channels ■ External interface via memory *For more details, please refer to the PDF document or feel free to contact us.

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The "Viterbi Decoder" is an FPGA IP core for Viterbi decoding that corresponds to convolutional codes, which are widely used as representative error correction coding schemes. It supports both soft decision decoding and hard decision decoding. It is compatible with constraint length 7 (171 oct, 133 oct) convolutional codes, which are standard in many communication standards including IEEE802.11a. It can be applied to various applications. 【Features】 ■ Achieves a maximum line speed of approximately 110 Mbps and is adaptable to the IEEE802.11a standard ■ Built-in de-puncturing function ■ Supports coding rates of 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, and 7/8 ■ Implements a speed conversion block corresponding to the coding rate ■ Configuration that does not use memory blocks (EAB) ■ Allows setting of the traceback length via parameters ■ Configurable soft decision bit width *For more details, please refer to the PDF document or feel free to contact us.

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The "SH3-compatible PCI Host Bridge" connects devices with a PCI interface to the local bus of the Renesas Electronics SH3. It is composed only of highly necessary functions, making it small in scale and easy to implement. 【Features】 ■ Compliant with PCI Rev 2.2 ■ Can be directly connected to the local bus of Renesas Electronics SH3 ■ Supports master/target operation ■ PCI devices can act as bus masters, enabling DMA transfers *For more details, please refer to the PDF document or feel free to contact us.

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The "PCM Codec" is a linear PCM codec IP for FPGA that complies with the ITU-T G.711 standard. By using general A/D and D/A, the risk of discontinuation can be reduced compared to commercially available PCM codec LSI. 【Features】 ■ Compliant with ITU-T G.711 ■ Capable of linear PCM ⇔ μ-law/A-law PCM conversion ■ Small circuit size allows for implementation in small-scale FPGAs *For more details, please refer to the PDF document or feel free to contact us.

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The "MPSC PLD" is an FPGA IP core for a multi-protocol serial controller (MPSC) aimed at being compatible with NEC's μPD72001. Like the uPD72001, it supports three types of protocols: synchronous, COP, and BOP. 【Features】 ■ It can replace systems using NEC's μPD72001 without significantly changing the control software. ■ Provided in RTL (VHDL) or FPGA ROM data. ■ Can be implemented on smaller and cheaper FPGAs limited to only the necessary protocols and channel counts (customization available). ■ Equipped with a 5V interface support function (external bus buffer control function for level conversion). *For more details, please refer to the PDF document or feel free to contact us.

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The "DES (TripleDES)" is an encryption/decryption engine IP core for the common key encryption DES, which processes 64-bit data as a unit. It can be customized according to customer requirements, including external control circuits, allowing for a reduction in the scale of the FPGA circuit. 【Features】 ■ The algorithm complies with the American National Standards Institute (ANSI X3.92) standard. ■ The usage modes of DES comply with the American National Standards Institute (ANSI X3.106) standards for ECB and CBC modes. ■ The usage modes of Triple-DES comply with the American National Standards Institute (ANSI X9.52) standards for TECB and TCBC modes. ■ Triple-DES allows for the selection of 2-key/3-key encryption keys. ■ The encryption/decryption engine for DES/Triple-DES is realized in one package. *For more details, please refer to the PDF document or feel free to contact us.

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The "AHB-Compatible PCI Host Bridge" is a PCI host bridge that connects the AMBA AHB and PCI bus, allowing various PCI devices to be easily utilized from AHB architecture systems. It is composed only of highly necessary functions, making it small in scale and easy to implement. 【Features】 ■ Compliant with PCI Rev 2.2 ■ Compliant with AMBA Specification Rev 2.0 ■ Supports master/target operation * Can support only master operation or only target operation as well * For more details, please refer to the PDF document or feel free to contact us.

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The "AES" is an FPGA IP core for the standard common key encryption/decryption engine based on the AES algorithm. It is a common key block cipher that processes data in 128-bit units, offering higher security than DES and faster performance than Triple-DES. The algorithm complies with the U.S. Federal Information Processing Standard (NIST FIPS-197). It supports three key lengths: AES-128, AES-192, and AES-256. 【Features】 ■ Compliant with NIST FIPS-197 ■ Encryption/decryption realized in one package ■ Supports ECB/CBC/CTR operation modes ■ Standard key expansion for 128-bit, 192-bit, and 256-bit ■ Achieves a maximum processing speed of approximately 110 Mbps, making it applicable for network security devices *For more details, please refer to the PDF document or feel free to contact us.

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The "ADPCM Transcoder" is an FPGA-targeted ADPCM transcoder core IP compliant with ITU-T Recommendation G.726. By combining it with a PCM codec, it can replace an ADPCM codec LSI. It is designed in Verilog-HDL. Please consult us regarding support in VHDL. Additionally, it can be provided as a macro (netlist) or in ROM format. 【Features】 ■ Compliant with ITU-T Recommendation G.726 ■ PCM coding 64kbps ⇔ 32kbps ADPCM conversion ■ Converts 64kbps × 1 channel to 32kbps × 2 channels ■ Operates with a sampling frequency of 8kHz clock ■ Independent circuits for encoder/decoder *For more details, please refer to the PDF materials or feel free to contact us.

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The "PCM codec with ADC control function" is a PCM codec IP for FPGA realized in combination with the Texas Instruments ADC IC (TLV320AIC11K). It is designed in Verilog-HDL. Please consult us regarding support in VHDL. Additionally, it can be provided as a macro (netlist) or in ROM format. 【Features】 ■ Compliant with ITU-T G.711 ■ Linear PCM ⇔ μ-law/A-law PCM conversion ■ Utilizes the built-in audio band filter circuit of TLV320AIC11K *For more details, please refer to the PDF materials or feel free to contact us.

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