2nd Web Seminar "High-Level Synthesis (HLS) and High-Level Verification (HLV) Seminar" ~Introducing the Benefits of HLS/HLV Integrated Environment Tools and Development Case Studies~

This will be our first publication on Ipros.
We will hold a sequel to the "High-Level Synthesis and High-Level Verification Process Seminar" that was conducted at the end of last year! In the previous session, we explained what high-level synthesis and high-level verification are, which can generate hardware description languages through operational descriptions in C language and other languages. In this sequel, we will focus on the utilization of the high-level synthesis (HLS) and high-level verification (HLV) integrated environment tool. Additionally, Siemens EDA, the vendor of this tool, will also participate as a speaker, and we will deliver this event in collaboration!
■ OKI IDS Session Overview
We will clearly explain the benefits of the high-level synthesis and high-level verification process using the HLS and HLV integrated environment tool, incorporating development case studies.
■ Siemens EDA Japan, Inc. Session Overview
"Accelerating Product Innovation with Catapult for High-Level Design"
We will introduce the overview of the high-level design and high-level verification platform Catapult, along with the latest successful case studies.
We sincerely look forward to your participation.

Date and time | Wednesday, Jul 12, 2023 02:00 PM ~ 03:00 PM |
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Entry fee | Free |
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